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| datasheet advance information dual-channel,triple 10-bit lvds transmitter 1 idtv105a confidential confidential general description the v105a lvds display interface transmitter is designed to support pixel data transmission between a video processing engine and a digital video display. the dual channel lvds output supports pixel rates up to 150 mhz, enabling compatib ility with 1080p and wuxga display resolutions. total 67-bit lvcmos/lvttl input is provided. the v105a converts the 67 bit parallel input data into two 5-pair lvds (low voltage differential signaling) serial data outputs, in odd/even pixel format. input data can be clocked on the rising or falling edge of the inpu t clock (selectable). in video applications the 35 data bits are normally divided into 10 bits for each r, g and b channel and 5 control bits (which includes vsync, hsync and de). features ? dual 32+3-bit lvttl input supports up to 150 mhz pixel rate. ? dual pixel, lvds output supports 150 mhz pixel rate (compatible with 1080p and wuxga resolution) ? internal pll requires no external loop filter ? selectable rising or falling clock edge for data alignment ? compatible with spread spectrum clock source ? reduced lvds output voltage swing mode (selectable) to minimize emi ? single 3.3 v supply ? low power consumption cmos design ? power down mode ? available in 144 pin lqfp package (14x14mm body size) block diagram data serializer 35 txa1+ txa1- txb1+ txb1- txc1+ txc1- txd1+ txd1- txe1+ txe1- ttl input data latch, bit mapper, demux data serializer ta1[9:0] tb1[9:0] tc1[9:0] res1[2:1] ta2[9:0] tb2[9:0] tc2[9:0] res2[2:1] hsync vsync de ctrl map r/f rs pd test clkin pll and device timing 10 10 10 2 10 10 10 2 3 35 txd2+ txd2- txe2+ txe2- txa2+ txa2- txb2+ txb2- txc2+ txc2- tclk1+ tclk1- tclk2+ tclk2- dual-channel,triple 10- bit lvds transmitter idtv105a 7121/3
idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 2 idtv105a 7121/3 confidential pin assignment tc26 tc27 vcc gnd tc28 tc29 hsync vsync de nc nc nc vcc gnd clkin nc res11 res12 res21 res22 r/f rs nc map ctrl1 ctrl0 ctrl2 nc nc pd test nc nc pgnd pvcc pdnd tc16 tc15 tc14 gnd vcc tc13 tc12 tc11 tc10 tb19 tb18 tb17 tb16 tb15 gnd vcc tb14 tb13 tb12 tb11 tb10 ta19 ta18 ta17 ta16 gnd vcc ta10 ta14 ta13 ta12 ta11 ta10 pgnd pvcc pgnd nc tc17 tc18 tc19 vcc gnd ta20 ta21 ta22 ta23 ta24 ta25 ta26 ta27 ta28 ta29 vcc gnd tb20 tb21 tb22 tb23 tb24 tb25 tb26 tb27 tb28 tb29 vcc gnd tc20 tc21 tc22 tc23 tc24 tc25 lgnd txa1- txa1+ txb1- txb1+ lvcc lgnd txc1- txc1+ tclk1- tclk1+ lvcc lgnd txd1- txd1+ txe1- txe1+ lvcc lgnd txa2- txa2+ txb2- txa2+ lvcc lgnd txc2- txc2+ tclk2- tclk2+ lvcc lgnd txd2- txd2+ txe2- txe2+ lgnd 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 v105a idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 3 idtv105a 7121/3 confidential pin descriptions pin number pin name pin type pin description 70, 71 txa1+, txa1- lvds out lvds serial data output pairs, channel 1 68, 69 txb1+, txb1- 64, 65 txc1+, txc1- 58, 59 txd1+, txd1- 56, 57 txe1+, txe1- 52, 53 txa2+, txa2- lvds serial data output pairs, channel 2 50,51 txb2+, txb2- 46, 47 txc2+, txc2- 40, 41 txd2+, txd2- 38,39 txe2+, txe2- 62, 63 tclk1+, tclk1- lvds out lvds reference clock output pair 44, 45 tclk2+, tclk2- 76, 77, 78, 79, 80, 81, 84, 85, 86, 87 ta10 ~ta19 in cmos/ttl (or small signal) data bit inputs, channel 1 88, 89, 90, 91, 92, 95, 96, 97, 98, 99 tb10 ~ tb19 100, 101, 102, 103, 106, 107, 108, 110, 111, 112 tc10 ~tc19 17, 18 res11, res12 in control input, channel 1 115, 116,117, 118, 119, 120, 121, 122, 123, 124 ta20 ~ ta29 in cmos/ttl (or small signal) data bit inputs, channel 2 127, 128, 129, 130, 131, 132, 133, 134, 135, 136 tb20 ~ tb29 139, 140, 141, 142, 143, 144, 1, 2, 5, 6 tc20 ~ tc29 19, 20 res21, res22 in control input, channel 2 7 hsync in hsync inputi 8 vsync in vsync input 9deinde input 25, 26, 27 ctrl0 ~ ctrl2 in mode selection 24 map in map mode selection 30 pd in high: normal device operation low: power down; all outputs become high impedance 31 test in reserved: tie to high or low idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 4 idtv105a 7121/3 confidential rs input voltage lvds output sw ing cmos/ttl input configuration (input voltage swing) 22 rs in voltage level on this pin sets lvds output swing voltage and data input swing voltage; refer to the table at the bottom of this page. 21 r/f in input clock triggering edge select. high: rising edge; low: falling edge. 3, 13,82, 93, 104, 113, 125, 137 v cc power power supply pins for ttl inputs and digital circuitry 15 clkin in clock input 4, 14, 83, 94, 105, 114, 126, 138 gnd ground ground pins for ttl inputs and digital circuitry 43, 49, 55, 61, 67 lv cc power power supply pins for lvds outputs 37, 42, 48, 54, 60, 66, 72 lgnd ground ground pins for lvds outputs 35, 74 pv cc power power supply pins for pll circuitry 34, 36, 73, 75 pgnd ground ground pins for pll circuitry 10, 11, 12, 16, 23, 28, 29, 32, 33, 109 nc reserved pin number pin name pin type pin description rs input voltage lvds output swing cmos/ttl input configuration (input voltage swing v cc 350 mv standard input and output configuration 1 0.6 ~ 1.4 v (v ref 1 ) 1. refer to dc electrical characteristics. 350 mv small input swing, standard output swing configuration 1 gnd 200 mv standard input swing, reduced output swing configuration 1 idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 5 idtv105a 7121/3 confidential external components decoupling capacitors should be used for all power pins. absolute maximum ratings recommended operation conditions item rating 1 supply voltage, v cc -0.3 v to +4.0 v cmos/ttl input voltage -0.3 v to v cc +0.3 v cmos/ttl output voltage -0.3 v to v cc +0.3 v lvds driver output voltage -0.3 v to v cc +0.3 v storage temperature -55 to +150c junction temperature +125c leadtemperature (10 seconds) +260c maximum power dissipation @ 25c 1.15 w 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this sp ecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability symbol parameter min. typ. max. units v cc power supply voltage +3 +3.3 +3.6 v ta ambient operating temperature 0 +70 c clk ctrl<1:0> = ll (d ual-in/dual-out) input 20 135 mhz lvds output 20 135 mhz ctrl<1:0> = lh (dual-in/single-out) input 10 67.5 mhz lvds output 20 135 mhz ctrl<1:0> = hl (single-in/dual-out) single edge input (ctrl<2> = l) input 40 150 mhz lvds output 20 75 mhz double edge input (ctrl<2> = h) input 20 135 mhz lvds output 20 135 mhz ctrl<1:0> = hh (single-in/single-out) distribution off (ctrl<2> = l) input 20 135 mhz lvds output 20 135 mhz distribution on (ctrl<2> = h) input 20 135 mhz lvds output 20 135 mhz idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 6 idtv105a 7121/3 confidential dc electrical characteristics v dd =3.3 v 10%, ambient temperature 0 to +70c parameter symbol conditions min. typ. max. units cmos/ttl inputs, standard configuration input high voltage v ih rs=v cc or gnd 2.00 v cc v input low voltage v il rs=v cc or gnd gnd 0.80 v input current i inc 0v idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 8 idtv105a 7121/3 confidential ac electrical characteristics v dd =3.3 v 10%, ambient temperature 0 to +70c, mode=135 mhz thermal characteristics parameter symbol min. typ. max. units switching characteristics clk in transition time t tcit 1.0 ns clk in period t tcp 6.7 100.0 ns clk in high time 1 1. see figure 1. t tch 2.59 3.7 4.81 ns clk in low time 1 t tcl 2.59 3.7 4.81 ns clk in to tclk delay t tcd 22.2 ns ttl data setup to clk in t ts 2.5 ns ttl data hold from clk in t th 0ns lvds transition time t lvt 0.6 1.5 ns output data position0 t top1 -0.2 0.0 0.2 ns output data position1 t top0 0.907 1.057 1.207 ns output data position2 t top6 1.814 2.114 2.414 ns output data position3 t top5 2.721 3.171 3.621 ns output data position4 t top4 3.628 4.228 4.828 ns output data position5 t top3 4.535 5.285 6.035 ns output data position6 t top2 5.442 6.342 7.242 ns phase lock loop set t tpll 10.0 ms parameter symbol conditions min. typ. max. units thermal resistance junction to ambient j a still air 53 c/w j a 1 m/s air flow 40 c/w j a 3 m/s air flow 33 c/w thermal resistance junction to case j c 8 c/w idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 9 idtv105a 7121/3 confidential ac timing diagrams figure 1. figure 2. t tcit . t tch 10% 90% clkin t tcit . 90% 10% t tcl t lvt 20% 80% t lvt 80% 20% v dif = (ta+) - (ta-) ta+ ta- 5pf 100 ? ttl input lvds output ttl inputs clkin txy0-txy9 vref t tch t tcp t tcl t ts v oc tclk+ t tcd note: clkin for r/f = gnd, solid line clkin for r/f = vcc, dashed line v ih or v sh v il or v sl t th tclk- vref v ih or v sh v il or v sl idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 10 idtv105a 7121/3 confidential figure 3. txa16 txa15 txa14 txa13 txa12 txa11 txa10 txa1 txb1 txc1 txd1 txe1 lvds output txb16 txb15 txb14 txb13 txb12 txb11 txb10 txc16 txc15 txc14 txc13 txc12 txc11 txc10 txd16 txd15 txd14 txd13 txd12 txd11 txd10 txe16 txe15 txe14 txe13 txe12 txe11 txe10 tclk1 out (differential) v dif = 0v previous cycle v dif = 0v next cycle t top1 t top0 t top6 t top5 t top4 t top3 t top2 idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 11 idtv105a 7121/3 confidential figure 4. txa26 txa25 txa24 txa23 txa22 txa21 txa20 txa2 txb2 txc2 txd2 txe2 lvds output txb16 txb25 txb24 txb23 txb22 txb21 txb20 txc26 txc25 txc24 txc23 txc22 txc21 txc20 txd26 txd25 txd24 txd23 txd22 txd21 txd20 txe26 txe25 txe24 txe23 txe22 txe21 txe20 tclk2 out (differential) v dif = 0v previous cycle v dif = 0v next cycle t top1 t top0 t top6 t top5 t top4 t top3 t top2 idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 12 idtv105a 7121/3 confidential figure 5. figure 6. phase lock loop time pd 2.0v v cc 3.0v clkin tclk1 tclk2 t tpll 3.6v v dif = 0v clkin 1st pixel lvds output data mapping v cc de gnd ta1n, tb1n, tc1n n = 0 - 9 hsync vsync res 11, 12 note: ctrl2 = h (double edge input) clkin for r/f = vcc, solid line clkin for r/f = g nd, dashed line single-in, dual-out ( ddr on) ctrl<2:0> = hhl single-in, dual-out (ddr off); mode<2:0> = lhl v cc gnd v cc gnd v cc gnd data ta1n, tb1n, tc1n n = 0 - 9 hsync vsync res 11, 12 2nd pixel data 1st pixel data 2nd pixel data 1st pixel data 2nd pixel data 1st pixel data 2nd pixel data 1st pixel data idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 13 idtv105a 7121/3 confidential single-in/ single-out distribution off: ctrl<2:0> = lhh lvds output data map = 1 map = 0 txa1[0] ta14 ta12 txa1[1] ta15 ta13 txa1[2] ta16 ta14 txa1[3] ta17 ta15 txa1[4] ta18 ta16 txa1[5] ta19 ta17 txa1[6] tb14 tb12 txb1[0] tb15 tb13 txb1[1] tb16 tb14 txb1[2] tb17 tb15 txb1[3] tb18 tb16 txb1[4] tb19 tb17 txb1[5] tc14 tc12 txb1[6] tc15 tc13 txc1[0] tc16 tc14 txc1[1] tc17 tc15 txc1[2] tc18 tc16 txc1[3] tc19 tc17 txc1[4] hsync hsync txc1[5] vsync vsync txc1[6] de de txd1[0] ta12 ta18 txd1[1] ta13 ta19 txd1[2] tb12 tb18 txd1[3] tb13 tb19 txd1[4] tc12 tc18 txd1[5] tc13 tc19 txd1[6] res11 res11 txe1[0] ta10 ta10 txe1[1] ta11 ta11 txe1[2] tb10 tb10 txe1[3] tb11 tb11 txe1[4] tc10 tc10 txe1[5] tc11 tc11 txe1[6] res12 res12 idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 14 idtv105a 7121/3 confidential single-in/ single-out distribution on: ctrl<2:0> = hhh first link second link lvds output data map = 1 map = 0 lvds output data map = 1 map = 0 txa1[0] ta14 ta12 txa2[0] ta14 ta12 txa1[1] ta15 ta13 txa2[1] ta15 ta13 txa1[2] ta16 ta14 txa2[2] ta16 ta14 txa1[3] ta17 ta15 txa2[3] ta17 ta15 txa1[4] ta18 ta16 txa2[4] ta18 ta16 txa1[5] ta19 ta17 txa2[5] ta19 ta17 txa1[6] tb14 tb12 txa2[6] tb14 tb12 txb1[0] tb15 tb13 txb2[0] tb15 tb13 txb1[1] tb16 tb14 txb2[1] tb16 tb14 txb1[2] tb17 tb15 txb2[2] tb17 tb15 txb1[3] tb18 tb16 txb2[3] tb18 tb16 txb1[4] tb19 tb17 txb2[4] tb19 tb17 txb1[5] tc14 tc12 txb2[5] tc14 tc12 txb1[6] tc15 tc13 txb2[6] tc15 tc13 txc1[0] tc16 tc14 txc2[0] tc16 tc14 txc1[1] tc17 tc15 txc2[1] tc17 tc15 txc1[2] tc18 tc16 txc2[2] tc18 tc16 txc1[3] tc19 tc17 txc2[3] tc19 tc17 txc1[4] hsync hsync txc2[4] hsync hsync txc1[5] vsync vsync txc2[5] vsync vsync txc1[6] de de txc2[6] de de txd1[0 ta12 ta18 txd2[0] ta12 ta18 txd1[1] ta13 ta19 txd2[1] ta13 ta19 txd1[2] tb12 tb18 txd2[2] tb12 tb18 txd1[3] tb13 tb19 txd2[3] tb13 tb19 txd1[4] tc12 tc18 txd2[4] tc12 tc18 txd1[5] tc13 tc19 txd2[5] tc13 tc19 txd1[6] res11 res11 txd2[6] res11 res11 txe1[0] ta10 ta10 txe2[0] ta10 ta10 txe1[1] ta11 ta11 txe2[1] ta11 ta11 txe1[2] tb10 tb10 txe2[2] tb10 tb10 txe1[3] tb11 tb11 txe2[3] tb11 tb11 txe1[4] tc10 tc10 txe2[4] tc10 tc10 txe1[5] tc11 tc11 txe2[5] tc11 tc11 txe1[6] res12 res12 txe2[6] res12 res12 idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 15 idtv105a 7121/3 confidential single-in/ dual-out ddr on or off: ctrl<2:0> = hhl or lhl first pixel data second pixel data lvds output data map = 1 map = 0 lvds output data map = 1 map = 0 txa1[0] ta14 ta12 txa2[0] ta14 ta12 txa1[1] ta15 ta13 txa2[1] ta15 ta13 txa1[2] ta16 ta14 txa2[2] ta16 ta14 txa1[3] ta17 ta15 txa2[3] ta17 ta15 txa1[4] ta18 ta16 txa2[4] ta18 ta16 txa1[5] ta19 ta17 txa2[5] ta19 ta17 txa1[6] tb14 tb12 txa2[6] tb14 tb12 txb1[0] tb15 tb13 txb2[0] tb15 tb13 txb1[1] tb16 tb14 txb2[1] tb16 tb14 txb1[2] tb17 tb15 txb2[2] tb17 tb15 txb1[3] tb18 tb16 txb2[3] tb18 tb16 txb1[4] tb19 tb17 txb2[4] tb19 tb17 txb1[5] tc14 tc12 txb2[5] tc14 tc12 txb1[6] tc15 tc13 txb2[6] tc15 tc13 txc1[0] tc16 tc14 txc2[0] tc16 tc14 txc1[1] tc17 tc15 txc2[1] tc17 tc15 txc1[2] tc18 tc16 txc2[2] tc18 tc16 txc1[3] tc19 tc17 txc2[3] tc19 tc17 txc1[4] hsync hsync txc2[4] hsync hsync txc1[5] vsync vsync txc2[5] vsync vsync txc1[6] de de txc2[6] de de txd1[0 ta12 ta18 txd2[0] ta12 ta18 txd1[1] ta13 ta19 txd2[1] ta13 ta19 txd1[2] tb12 tb18 txd2[2] tb12 tb18 txd1[3] tb13 tb19 txd2[3] tb13 tb19 txd1[4] tc12 tc18 txd2[4] tc12 tc18 txd1[5] tc13 tc19 txd2[5] tc13 tc19 txd1[6] res11 res11 txd2[6] res11 res11 txe1[0] ta10 ta10 txe2[0] ta10 ta10 txe1[1] ta11 ta11 txe2[1] ta11 ta11 txe1[2] tb10 tb10 txe2[2] tb10 tb10 txe1[3] tb11 tb11 txe2[3] tb11 tb11 txe1[4] tc10 tc10 txe2[4] tc10 tc10 txe1[5] tc11 tc11 txe2[5] tc11 tc11 txe1[6] res12 res12 t xe2[6] res12 res12 idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 16 idtv105a 7121/3 confidential dual-in/ single-out: ct rl<2:0> = hlh or llh first pixel data second pixel data lvds output data map = 1 map = 0 lvds output data map = 1 map = 0 txa1[0](n) ta14 ta12 txa1[0](n+1) ta24 ta22 txa1[1](n) ta15 ta13 txa1[1](n+1) ta25 ta23 txa1[2](n) ta16 ta14 txa1[2(]n+1) ta26 ta24 txa1[3](n) ta17 ta15 txa1[3](n+1) ta27 ta25 txa1[4](n) ta18 ta16 txa1[4](n+1) ta28 ta26 txa1[5](n) ta19 ta17 txa1[5](n+1) ta29 ta27 txa1[6](n) tb14 tb12 txa1[6](n+1) tb24 tb22 txb1[0](n) tb15 tb13 txb1[0](n+1) tb25 tb23 txb1[1](n) tb16 tb14 txb1[1](n+1) tb26 tb24 txb1[2](n) tb17 tb15 txb1[2](n+1) tb27 tb25 txb1[3](n) tb18 tb16 txb1[3](n+1) tb28 tb26 txb1[4](n) tb19 tb17 txb1[4](n+1) tb29 tb27 txb1[5](n) tc14 tc12 txb1[5](n+1) tc24 tc22 txb1[6](n) tc15 tc13 txb1[6](n+1) tc25 tc23 txc1[0](n) tc16 tc14 txc1[0](n+1) tc26 tc24 txc1[1](n) tc17 tc15 txc1[1](n+1) tc27 tc25 txc1[2](n) tc18 tc16 txc1[2](n+1) tc28 tc26 txc1[3](n) tc19 tc17 txc1[3](n+1) tc29 tc27 txc1[4](n) hsync hsync t xc1[4](n+1) hsync hsync txc1[5](n) vsync vsync txc1[5](n+1) vsync vsync txc1[6](n) de de txc1[6](n+1) de de txd1[0](n) ta12 ta18 txd1[0](n+1) ta22 ta28 txd1[1](n) ta13 ta19 txd1[1](n+1) ta23 ta29 txd1[2](n) tb12 tb18 txd1[2](n+1) tb22 tb28 txd1[3](n) tb13 tb19 txd1[3](n+1) tb23 tb29 txd1[4](n) tc12 tc18 txd1[4](n+1) tc22 tc28 txd1[5](n) tc13 tc19 txd1[5](n+1) tc23 tc29 txd1[6](n) res11 res11 t xd1[6](n+1) res21 res21 txe1[0](n) ta10 ta10 txe1[0](n+1) ta20 ta20 txe1[1](n) ta11 ta11 txe1[1](n+1) ta21 ta21 txe1[2](n) tb10 tb10 txe1[2](n+1) tb20 tb20 txe1[3](n) tb11 tb11 txe1[3](n+1) tb21 tb21 txe1[4](n) tc10 tc10 txe1[4](n+1) tc20 tc20 txe1[5](n) tc11 tc11 txe1[5](n+1) tc21 tc21 txe1[6](n) res12 res12 t xe1[6](n+1) res22 res22 idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 17 idtv105a 7121/3 confidential dual-in/ dual-out: ctrl<2:0> = hll or lll first pixel data second pixel data lvds output data map = 1 map = 0 lvds output data map = 1 map = 0 txa1[0] ta14 ta12 txa2[0] ta24 ta22 txa1[1] ta15 ta13 txa2[1] ta25 ta23 txa1[2] ta16 ta14 txa2[2] ta26 ta24 txa1[3] ta17 ta15 txa2[3] ta27 ta25 txa1[4] ta18 ta16 txa2[4] ta28 ta26 txa1[5] ta19 ta17 txa2[5] ta29 ta27 txa1[6] tb14 tb12 txa2[6] tb24 tb22 txb1[0] tb15 tb13 txb2[0] tb25 tb23 txb1[1] tb16 tb14 txb2[1] tb26 tb24 txb1[2] tb17 tb15 txb2[2] tb27 tb25 txb1[3] tb18 tb16 txb2[3] tb28 tb26 txb1[4] tb19 tb17 txb2[4] tb29 tb27 txb1[5] tc14 tc12 txb2[5] tc24 tc22 txb1[6] tc15 tc13 txb2[6] tc25 tc23 txc1[0] tc16 tc14 txc2[0] tc26 tc24 txc1[1] tc17 tc15 txc2[1] tc27 tc25 txc1[2] tc18 tc16 txc2[2] tc28 tc26 txc1[3] tc19 tc17 txc2[3] tc29 tc27 txc1[4] hsync hsync txc2[4] hsync hsync txc1[5] vsync vsync txc2[5] vsync vsync txc1[6] de de txc2[6] de de txd1[0 ta12 ta18 txd2[0] ta22 ta28 txd1[1] ta13 ta19 txd2[1] ta23 ta29 txd1[2] tb12 tb18 txd2[2] tb22 tb28 txd1[3] tb13 tb19 txd2[3] tb23 tb29 txd1[4] tc12 tc18 txd2[4] tc22 tc28 txd1[5] tc13 tc19 txd2[5] tc23 tc29 txd1[6] res11 res11 txd2[6] res21 res21 txe1[0] ta10 ta10 txe2[0] ta20 ta20 txe1[1] ta11 ta11 txe2[1] ta21 ta21 txe1[2] tb10 tb10 txe2[2] tb20 tb20 txe1[3] tb11 tb11 txe2[3] tb21 tb21 txe1[4] tc10 tc10 txe2[4] tc20 tc20 txe1[5] tc11 tc11 txe2[5] tc21 tc21 txe1[6] res12 res12 t xe2[6] res22 res22 idtv105a dual-channel,triple 10-bit lvds transmi tter commercial temperature range dual-channel,triple 10-bit lvds transmitter 18 idtv105a 7121/3 confidential package outline and package dimensions (144-pin lqfp) package dimensions are kept current with jedec publication no. 95, variation acd. index area n e2 e1 e d d1 ref. d2 ref. 1 2 3 l e ccc c a a2 a1 b c sealing plate -c- all dimensions are in millimeters. symbol in millimeters common dimensions in inches 1 common dimensions min max min max n 144 144 a ? 1.60 ? .063 a1 0.05 0.15 .002 .006 a2 1.35 1.45 .053 .057 b 0.170.27.007.011 c 0.090.20.004.008 d 22.00 basic .866 basic d1 20.00 basic .787 basic d2 17.50 ref. .689 ref. e 22.00 basic .866 basic e1 20.00 basic .787 basic e2 17.50 ref. .689 ref. e 0.50 basic .02 basic l 0.450.75.018 .03 q0707 ccc ? 0.08 ? .003 1. for reference only. controlling dimensions are in mm. idtv105a dual-channel,triple 10-bit lvds tr ansmitter commercial temperature range ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: videohelp@idt.com ordering information idt xxxx device type x package x temp. range x shipping carrier 8 blank dag v105a tape and reel commercial (0c to +70c) dual-channe, triple 10-bit lvds transmitter thin quad flat pack - green |
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